{
  'attributes' => {
    'HDLCodeGenStatus' => 0,
    'HDL_PATH' => 'G:/Work/FPGA_CD/chapt8/exp8_5',
    'TEMP' => 'C:/TEMP',
    'TMP' => 'C:/TEMP',
    'Temp' => 'C:/TEMP',
    'Tmp' => 'C:/TEMP',
    'base_system_period_hardware' => 20,
    'base_system_period_simulink' => 1,
    'block_icon_display' => 'Default',
    'block_type' => 'sysgen',
    'block_version' => '',
    'ce_clr' => 0,
    'clkWrapper' => 'exp_chipscope_cw',
    'clkWrapperFile' => 'exp_chipscope_cw.vhd',
    'clock_domain' => 'default',
    'clock_loc' => 'P56',
    'clock_wrapper' => 'Clock Enables',
    'clock_wrapper_sgadvanced' => '',
    'compilation' => 'Bitstream',
    'compilation_lut' => {
      'keys' => [
        'HDL Netlist',
        'Bitstream',
      ],
      'values' => [
        'target1',
        'target2',
      ],
    },
    'compilation_target' => 'Bitstream',
    'core_generation' => 1,
    'core_generation_sgadvanced' => '',
    'core_is_deployed' => 0,
    'coregen_core_generation_tmpdir' => 'C:/TEMP/sysgentmp-Administrator/cg_wk/c5302b271738f5c8a',
    'coregen_part_family' => 'spartan6',
    'createTestbench' => 0,
    'create_interface_document' => 'off',
    'dbl_ovrd' => -1,
    'dbl_ovrd_sgadvanced' => '',
    'dcm_info' => {
    },
    'dcm_input_clock_period' => 10,
    'deprecated_control' => 'off',
    'deprecated_control_sgadvanced' => '',
    'design' => 'exp_chipscope',
    'designFile' => 'exp_chipscope.vhd',
    'design_full_path' => 'G:\\Work\\FPGA_CD\\chapt8\\exp8_5\\exp_chipscope.mdl',
    'device' => 'xc6slx9-2tqg144',
    'device_speed' => -2,
    'directory' => 'G:/Work/FPGA_CD/chapt8/exp8_5/netlist',
    'dsp_cache_root_path' => 'C:/TEMP/sysgentmp-Administrator',
    'entityNamingInstrs' => {
      'nameMap' => undef,
      'namesAlreadyUsed' => {
        'default_clock_driver' => 1,
        'exp_chipscope_cw' => 1,
      },
    },
    'eval_field' => 0,
    'fileAttributes' => {
      'dds_cmplr_v4_0_f34617d41a297694.ngc' => {
        'producer' => 'coregen',
      },
      'icon_1_05_a_1b7f349aaf57f307.ngc' => {
        'producer' => 'coregen',
      },
      'ila_1_04_a_931ec98e70229a14.ngc' => {
        'producer' => 'coregen',
      },
    },
    'files' => [
      'dds_cmplr_v4_0_f34617d41a297694.ngc',
      'icon_1_05_a_1b7f349aaf57f307.ngc',
      'ila_1_04_a_931ec98e70229a14.ngc',
      'xlpersistentdff.ngc',
      'synopsis',
      'exp_chipscope.vhd',
      'xlpersistentdff.ngc',
      'exp_chipscope_cw.vhd',
      'exp_chipscope_cw.ucf',
      'exp_chipscope_cw.xcf',
      'exp_chipscope_cw.sdc',
      'xst_exp_chipscope.prj',
      'xst_exp_chipscope.scr',
      'vcom.do',
      'isim_exp_chipscope.prj',
      'globals',
      'hdlFiles',
      'exp_chipscope_cw.xise',
      'exp_chipscope_cw.gise',
      'exp_chipscope_cw.sgp',
    ],
    'fxdptinstalled' => 1,
    'generateUsing71FrontEnd' => 1,
    'generating_island_subsystem_handle' => 2074.00122070313,
    'generating_subsystem_handle' => 2074.00122070313,
    'generation_directory' => './netlist',
    'has_advanced_control' => 0,
    'hdlDir' => 'G:/Software/ISE_DS/ISE/sysgen/hdl',
    'hdlKind' => 'vhdl',
    'hdl_path' => 'G:/Work/FPGA_CD/chapt8/exp8_5',
    'incr_netlist' => 'off',
    'incr_netlist_sgadvanced' => '',
    'infoedit' => ' System Generator',
    'isdeployed' => 0,
    'ise_version' => '13.2i',
    'master_sysgen_token_handle' => 2075.01611328125,
    'matlab' => 'G:/Program Files/Matlab',
    'matlab_fixedpoint' => 1,
    'mdlHandle' => 2074.00122070313,
    'mdlPath' => 'G:/Work/FPGA_CD/chapt8/exp8_5/exp_chipscope.mdl',
    'modelDiagnostics' => [
      {
        'count' => 9,
        'isMask' => 0,
        'type' => 'exp_chipscope Total blocks',
      },
      {
        'count' => 2,
        'isMask' => 0,
        'type' => 'DiscretePulseGenerator',
      },
      {
        'count' => 3,
        'isMask' => 0,
        'type' => 'S-Function',
      },
      {
        'count' => 1,
        'isMask' => 0,
        'type' => 'Scope',
      },
      {
        'count' => 1,
        'isMask' => 0,
        'type' => 'SubSystem',
      },
      {
        'count' => 2,
        'isMask' => 0,
        'type' => 'Terminator',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx ChipScope Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx DDS Compiler 4.0 Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx Gateway Out Block',
      },
      {
        'count' => 1,
        'isMask' => 1,
        'type' => 'Xilinx System Generator Block',
      },
    ],
    'model_globals_initialized' => 1,
    'model_path' => 'G:/Work/FPGA_CD/chapt8/exp8_5/exp_chipscope.mdl',
    'myxilinx' => 'G:/Software/ISE_DS/ISE',
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
    'ngc_files' => [
      'xlpersistentdff.ngc',
    ],
    'num_sim_cycles' => 100000,
    'package' => 'tqg144',
    'part' => 'xc6slx9',
    'partFamily' => 'spartan6',
    'port_data_types_enabled' => 0,
    'postgeneration_fcn' => 'xlBitstreamPostGeneration',
    'preserve_hierarchy' => 0,
    'proj_type' => 'Project Navigator',
    'proj_type_sgadvanced' => '',
    'run_coregen' => 'off',
    'run_coregen_sgadvanced' => '',
    'sample_time_colors_enabled' => 0,
    'sampletimecolors' => 0,
    'sdcFile' => 'exp_chipscope_cw.sdc',
    'settings_fcn' => 'xlTopLevelNetlistGUI',
    'sg_blockgui_xml' => '',
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
    'sg_list_contents' => '',
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');',
    'sg_version' => '',
    'sggui_pos' => '-1,-1,-1,-1',
    'simulation_island_subsystem_handle' => 2074.00122070313,
    'simulinkName' => 'parking_lot',
    'simulink_accelerator_running' => 0,
    'simulink_debugger_running' => 0,
    'simulink_period' => 1,
    'speed' => -2,
    'synthesisTool' => 'XST',
    'synthesis_language' => 'vhdl',
    'synthesis_tool' => 'XST',
    'synthesis_tool_sgadvanced' => '',
    'sysclk_period' => 20,
    'sysgen' => 'G:/Software/ISE_DS/ISE/sysgen',
    'sysgenRoot' => 'G:/Software/ISE_DS/ISE/sysgen',
    'sysgenTokenSettings' => {
      'base_system_period_hardware' => 20,
      'base_system_period_simulink' => 1,
      'block_icon_display' => 'Default',
      'block_type' => 'sysgen',
      'block_version' => '',
      'ce_clr' => 0,
      'clock_loc' => 'P56',
      'clock_wrapper' => 'Clock Enables',
      'clock_wrapper_sgadvanced' => '',
      'compilation' => 'Bitstream',
      'compilation_lut' => {
        'keys' => [
          'HDL Netlist',
          'Bitstream',
        ],
        'values' => [
          'target1',
          'target2',
        ],
      },
      'core_generation' => 1,
      'core_generation_sgadvanced' => '',
      'coregen_part_family' => 'spartan6',
      'create_interface_document' => 'off',
      'dbl_ovrd' => -1,
      'dbl_ovrd_sgadvanced' => '',
      'dcm_input_clock_period' => 10,
      'deprecated_control' => 'off',
      'deprecated_control_sgadvanced' => '',
      'directory' => './netlist',
      'eval_field' => 0,
      'has_advanced_control' => 0,
      'incr_netlist' => 'off',
      'incr_netlist_sgadvanced' => '',
      'infoedit' => ' System Generator',
      'master_sysgen_token_handle' => 2075.01611328125,
      'package' => 'tqg144',
      'part' => 'xc6slx9',
      'postgeneration_fcn' => 'xlBitstreamPostGeneration',
      'preserve_hierarchy' => 0,
      'proj_type' => 'Project Navigator',
      'proj_type_sgadvanced' => '',
      'run_coregen' => 'off',
      'run_coregen_sgadvanced' => '',
      'settings_fcn' => 'xlTopLevelNetlistGUI',
      'sg_blockgui_xml' => '',
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
      'sg_list_contents' => '',
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
fprintf(\'\',\'COMMENT: end icon graphics\');
fprintf(\'\',\'COMMENT: begin icon text\');
fprintf(\'\',\'COMMENT: end icon text\');',
      'sggui_pos' => '-1,-1,-1,-1',
      'simulation_island_subsystem_handle' => 2074.00122070313,
      'simulink_period' => 1,
      'speed' => -2,
      'synthesis_language' => 'vhdl',
      'synthesis_tool' => 'XST',
      'synthesis_tool_sgadvanced' => '',
      'sysclk_period' => 20,
      'testbench' => 0,
      'testbench_sgadvanced' => '',
      'trim_vbits' => 1,
      'trim_vbits_sgadvanced' => '',
      'version' => 11.2,
      'xilinx_device' => 'xc6slx9-2tqg144',
      'xilinxfamily' => 'spartan6',
    },
    'sysgen_Root' => 'G:/Software/ISE_DS/ISE/sysgen',
    'systemClockPeriod' => 20,
    'tempdir' => 'C:/TEMP',
    'testbench' => 0,
    'testbench_sgadvanced' => '',
    'tmpDir' => 'G:/Work/FPGA_CD/chapt8/exp8_5/netlist/sysgen',
    'trim_vbits' => 1,
    'trim_vbits_sgadvanced' => '',
    'ucfFile' => 'exp_chipscope_cw.ucf',
    'use_strict_names' => 1,
    'user_tips_enabled' => 0,
    'usertemp' => 'C:/TEMP/sysgentmp-Administrator',
    'using71Netlister' => 1,
    'verilog_files' => [
      'conv_pkg.v',
      'synth_reg.v',
      'synth_reg_w_init.v',
      'convert_type.v',
    ],
    'version' => 11.2,
    'vhdl_files' => [
      'conv_pkg.vhd',
      'synth_reg.vhd',
      'synth_reg_w_init.vhd',
    ],
    'vsimtime' => '2200275.000000 ns',
    'xcfFile' => 'exp_chipscope_cw.xcf',
    'xilinx' => 'G:/Software/ISE_DS/ISE',
    'xilinx_device' => 'xc6slx9-2tqg144',
    'xilinx_family' => 'spartan6',
    'xilinx_package' => 'tqg144',
    'xilinx_part' => 'xc6slx9',
    'xilinxdevice' => 'xc6slx9-2tqg144',
    'xilinxfamily' => 'spartan6',
    'xilinxpart' => 'xc6slx9',
  },
  'entityName' => '',
  'nets' => {
    '.clk' => {
      'hdlType' => 'std_logic',
      'width' => 1,
    },
    'sysgen_dut.gateway_out' => {
      'hdlType' => 'std_logic_vector(11 downto 0)',
      'width' => 12,
    },
  },
  'subblocks' => {
    'gateway_out' => {
      'connections' => {
        'gateway_out' => 'sysgen_dut.gateway_out',
      },
      'entity' => {
        'attributes' => {
          'entityAlreadyNetlisted' => 1,
          'isGateway' => 1,
          'is_floating_block' => 1,
        },
        'entityName' => 'gateway_out',
        'ports' => {
          'gateway_out' => {
            'attributes' => {
              'bin_pt' => 11,
              'inputFile' => 'exp_chipscope_gateway_out.dat',
              'is_floating_block' => 1,
              'is_gateway_port' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 1,
              'port_id' => 0,
              'simulinkName' => 'exp_chipscope/Gateway Out/Gateway Out',
              'source_block' => 'exp_chipscope/Gateway Out',
              'timingConstraint' => 'none',
              'type' => 'Fix_12_11',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic_vector(11 downto 0)',
            'width' => 12,
          },
        },
      },
      'entityName' => 'gateway_out',
    },
    'sysgen_dut' => {
      'connections' => {
        'clk' => '.clk',
        'gateway_out' => 'sysgen_dut.gateway_out',
      },
      'entity' => {
        'attributes' => {
          'entityAlreadyNetlisted' => 1,
          'hdlArchAttributes' => [
          ],
          'hdlEntityAttributes' => [
          ],
          'isClkWrapper' => 1,
        },
        'connections' => {
          'clk' => 'clkNet',
          'gateway_out' => 'gateway_out_net',
        },
        'entityName' => 'exp_chipscope_cw',
        'nets' => {
          'ce_1_sg_x0' => {
            'attributes' => {
              'hdlNetAttributes' => [
                [
                  'MAX_FANOUT',
                  'string',
                  '"REDUCE"',
                ],
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'clkNet' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'clk_1_sg_x0' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'gateway_out_net' => {
            'attributes' => {
              'hdlNetAttributes' => [
              ],
            },
            'hdlType' => 'std_logic_vector(11 downto 0)',
            'width' => 12,
          },
          'persistentdff_inst_q' => {
            'attributes' => {
              'hdlNetAttributes' => [
                [
                  'syn_keep',
                  'boolean',
                  'true',
                ],
                [
                  'keep',
                  'boolean',
                  'true',
                ],
                [
                  'preserve_signal',
                  'boolean',
                  'true',
                ],
              ],
            },
            'hdlType' => 'std_logic',
            'width' => 1,
          },
        },
        'ports' => {
          'ce' => {
            'attributes' => {
              'defaultHdlValue' => '\'1\'',
              'domain' => 'default',
              'group' => 0,
              'isCe' => 1,
              'period' => 1,
            },
            'direction' => 'in',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'clk' => {
            'attributes' => {
              'domain' => 'default',
              'group' => 0,
              'iobMap' => [
                'P56',
              ],
              'isClk' => 1,
              'period' => 1,
              'type' => 'logic',
            },
            'direction' => 'in',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
          'gateway_out' => {
            'attributes' => {
              'bin_pt' => 11,
              'inputFile' => 'exp_chipscope_gateway_out.dat',
              'is_floating_block' => 1,
              'is_gateway_port' => 1,
              'must_be_hdl_vector' => 1,
              'period' => 1,
              'port_id' => 0,
              'simulinkName' => 'exp_chipscope/Gateway Out/Gateway Out',
              'source_block' => 'exp_chipscope/Gateway Out',
              'timingConstraint' => 'none',
              'type' => 'Fix_12_11',
            },
            'direction' => 'out',
            'hdlType' => 'std_logic_vector(11 downto 0)',
            'width' => 12,
          },
        },
        'subblocks' => {
          'default_clock_driver_x0' => {
            'connections' => {
              'ce_1' => 'ce_1_sg_x0',
              'clk_1' => 'clk_1_sg_x0',
              'sysce' => [
                'constant',
                '\'1\'',
              ],
              'sysce_clr' => [
                'constant',
                '\'0\'',
              ],
              'sysclk' => 'clkNet',
            },
            'entity' => {
              'attributes' => {
                'domain' => 'default',
                'hdlArchAttributes' => [
                  [
                    'syn_noprune',
                    'boolean',
                    'true',
                  ],
                  [
                    'optimize_primitives',
                    'boolean',
                    'false',
                  ],
                  [
                    'dont_touch',
                    'boolean',
                    'true',
                  ],
                ],
                'hdlEntityAttributes' => [
                ],
                'isClkDriver' => 1,
              },
              'entityName' => 'default_clock_driver',
              'ports' => {
                'ce_1' => {
                  'attributes' => {
                    'domain' => 'default',
                    'group' => 1,
                    'isCe' => 1,
                    'period' => 1,
                    'type' => 'logic',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'clk_1' => {
                  'attributes' => {
                    'domain' => 'default',
                    'group' => 1,
                    'isClk' => 1,
                    'period' => 1,
                    'type' => 'logic',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'sysce' => {
                  'attributes' => {
                    'group' => 0,
                    'isCe' => 1,
                    'period' => 1,
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'sysce_clr' => {
                  'attributes' => {
                    'group' => 0,
                    'isClr' => 1,
                    'period' => 1,
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'sysclk' => {
                  'attributes' => {
                    'group' => 0,
                    'isClk' => 1,
                    'period' => 1,
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
              },
            },
            'entityName' => 'default_clock_driver',
          },
          'exp_chipscope_x0' => {
            'connections' => {
              'ce_1' => 'ce_1_sg_x0',
              'clk_1' => 'clk_1_sg_x0',
              'gateway_out' => 'gateway_out_net',
            },
            'entity' => {
              'attributes' => {
                'entityAlreadyNetlisted' => 1,
                'hdlKind' => 'vhdl',
                'isDesign' => 1,
                'simulinkName' => 'exp_chipscope',
              },
              'entityName' => 'exp_chipscope',
              'ports' => {
                'ce_1' => {
                  'attributes' => {
                    'domain' => '',
                    'group' => 1,
                    'isCe' => 1,
                    'is_subsys_port' => 1,
                    'period' => 1,
                    'subsys_port_index' => 0,
                    'type' => 'logic',
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'clk_1' => {
                  'attributes' => {
                    'domain' => '',
                    'group' => 1,
                    'isClk' => 1,
                    'is_subsys_port' => 1,
                    'period' => 1,
                    'subsys_port_index' => 0,
                    'type' => 'logic',
                  },
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'gateway_out' => {
                  'attributes' => {
                    'bin_pt' => 11,
                    'inputFile' => 'exp_chipscope_gateway_out.dat',
                    'is_floating_block' => 1,
                    'is_gateway_port' => 1,
                    'must_be_hdl_vector' => 1,
                    'period' => 1,
                    'port_id' => 0,
                    'simulinkName' => 'exp_chipscope/Gateway Out',
                    'source_block' => 'exp_chipscope',
                    'timingConstraint' => 'none',
                    'type' => 'Fix_12_11',
                  },
                  'direction' => 'out',
                  'hdlType' => 'std_logic_vector(11 downto 0)',
                  'width' => 12,
                },
              },
            },
            'entityName' => 'exp_chipscope',
          },
          'persistentdff_inst' => {
            'connections' => {
              'clk' => 'clkNet',
              'd' => 'persistentdff_inst_q',
              'q' => 'persistentdff_inst_q',
            },
            'entity' => {
              'attributes' => {
                'entityAlreadyNetlisted' => 1,
                'hdlCompAttributes' => [
                  [
                    'syn_black_box',
                    'boolean',
                    'true',
                  ],
                  [
                    'box_type',
                    'string',
                    '"black_box"',
                  ],
                ],
                'is_persistent_dff' => 1,
                'needsComponentDeclaration' => 1,
              },
              'entityName' => 'xlpersistentdff',
              'ports' => {
                'clk' => {
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'd' => {
                  'direction' => 'in',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
                'q' => {
                  'direction' => 'out',
                  'hdlType' => 'std_logic',
                  'width' => 1,
                },
              },
            },
            'entityName' => 'xlpersistentdff',
          },
        },
      },
      'entityName' => 'exp_chipscope_cw',
    },
    'sysgen_gw_clk' => {
      'connections' => {
        'clk' => '.clk',
      },
      'entity' => {
        'attributes' => {
          'entityAlreadyNetlisted' => 1,
          'isClk' => 1,
          'isGateway' => 1,
          'is_floating_block' => 1,
        },
        'entityName' => 'sysgen_gw_clk',
        'ports' => {
          'clk' => {
            'attributes' => {
              'isClk' => 1,
            },
            'direction' => 'out',
            'hdlType' => 'std_logic',
            'width' => 1,
          },
        },
      },
      'entityName' => 'sysgen_gw_clk',
    },
  },
}
